ANI Photo | Rajeev Chandrasekhar to participate in ‘Digital India RISC-V’ symposium at IIT Madras

Union Minister of State for Electronics and IT,  Rajeev Chandrasekhar, will attend the ‘Digital India RISC-V’ Symposium organized by IIT Madras and IIT-M Pravartak Technologies Foundation on Sunday in Chennai.
The symposium centred around ‘The future of Electronics in India through the RISC-V pathway,’ is expected to draw students, industry professionals, researchers, and enthusiasts keen on exploring the growing RISC-V ecosystem in India, a statement said.
Rajeev Chandrasekhar, along with IIT Madras Director Professor V Kamakoti and other dignitaries will address the event, sharing valuable insights and perspectives.
The symposium will feature insightful tech talks by academicians and industry experts, interactive stalls showcasing indigenous RISC-V processors, an engaging Hackathon and a special investor session.
‘RISC’ stands for ‘Reduced Instruction Set Computer’ and ‘V’ stands for the fifth generation. The RISC-V project began in 2010.
The RISC-V ISA enables a new era of processor innovation through open standard collaboration and aims to deliver a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
Prof Kamakoti developed ‘SHAKTI,’ India’s first indigenously-designed microprocessor based on RISC-V ISA.
The RISC-V foundation was formed in 2015 with IIT Madras being one of the founder members.
The DIR-V (Digital India RISC-V) Microprocessor Program was launched in 2022 by the GOI, with an overall aim to enable the creation of Microprocessors for the future in India, for the world and achieve industry-grade silicon & Design wins by December 2023.
The RISC-V ISA based designs are used by many companies and start-ups. It is open source and free of cost.
For academicians, the pedagogy of RISC-V ISA opens up an industry-relevant curriculum with numerous exciting research and applications. (ANI)

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